Improved planarization techniques applied to a low dielectric constant polyimide used in multilevel metal ICs

機譯：應用于多級金屬IC的低介電常數聚酰亞胺的改良平面化技術

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Abstract: A low dielectric constant fluorinated polyimide hasbeen employed as the interlevel dielectric in afour-level metal VLSI process. Due to the stringentrequirement of a near global planar topography comparedwith the partial planarizing properties of thepolyimide, two advanced approaches were evaluated: (1)a `negative-image' sacrificial photoresist etchbackprocess, and (2) a photoresist image reversal plus dryetch process. Both techniques remove the polyimide fromthe surface of the metal while leaving polyimide`islands' or `plugs' between the metal features. Asecond polyimide layer is then applied. The planarityof the finished structure is controlled by thethickness of the initial polyimide layer, the plasmaetch process, and the planarizing characteristics ofthe second or `recoat' polyimide film. The improvedglobal planarity achievable using the advancedtechniques were compared to a standard single spinpolyimide process using surface profilometer profilesand cross-sectional SEM micrographs. The pros and consof the two planarization techniques are also discussed.!12

機譯：摘要：低介電常數的氟化聚酰亞胺被用作四層金屬VLSI工藝中的層間電介質。由于與聚酰亞胺的局部平坦化性質相比，近乎全局的平面形貌的嚴格要求，評估了兩種先進的方法：（1）“負像”犧牲性光刻膠回蝕工藝，以及（2）光刻膠圖像反轉加干法蝕刻工藝。兩種技術都從金屬表面去除了聚酰亞胺，同時在金屬特征之間留有聚酰亞胺“島”或“塞子”。然后施加第二聚酰亞胺層。最終結構的平面度受初始聚酰亞胺層的厚度，等離子蝕刻工藝以及第二或“重涂”聚酰亞胺膜的平面化特性控制。使用表面輪廓儀輪廓和橫截面SEM顯微照片，將使用先進技術可獲得的改進的整體平面度與標準的單旋轉聚酰亞胺工藝進行了比較。還討論了兩種平面化技術的優缺點。！12

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《Metallization: Performance and Reliability Issues for VLSI and ULSI》|1991年|p.34-45|共12頁
會議地點 San Jose CA(US);San Jose CA(US)
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Author(s): Li-Hsin Chang Motorola Advanced Technology Ctr. Chandler AZ USA; Ray Goodner Motorola Advanced Technology Ctr. Mesa AZ USA.;
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正文語種 eng
中圖分類 TN;
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入庫時間 2022-08-26 13:44:17

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1. Planarization of dielectric layers for multilevel metallization [J] . Riley P.E., Castel E.D. IEEE Transactions on Semiconductor Manufacturing . 1988,第4期

機譯：用于多層金屬化的介電層的平面化
2. Novel Dielectric-Constant Evaluation Method for Low-$k$ Multilevel Metallization Structures in ULSI [J] . Takimoto Y., Maeda N. Semiconductor Manufacturing, IEEE Transactions on . 2009,第2期

機譯：ULSI中低$ k $多層金屬化結構的介電常數評估新方法
3. Low dielectric constant polyimide mixtures fabricated by polyimide matrix and polyimide microsphere fillers [J] . Polymer international . 2020,第5期

機譯：由聚酰亞胺基質和聚酰亞胺微球填充物制造的低介電常數聚酰亞胺混合物
4. Improved planarization techniques applied to a low dielectric constantpolyimide used in multilevel metal ICs, [C] . Li-Hsin Chang, Motorola Advanced Technology Ctr., Chandler, Metallization: Performance and Reliability Issues for VLSI and ULSI . 1991

機譯：應用于多級金屬IC中的低介電常數聚酰亞胺的改良平面化技術，
5. Investigations of the low-dielectric-constant fluorinated polyimide for use as the interlayer dielectric in ULSI. [D] . Lee, Yong Keun. 1996

機譯：低介電常數的氟化聚酰亞胺用作ULSI中的層間電介質的研究。
6. Synthesis of Superheat-Resistant Polyimides with Enhanced Dielectric Constant by Introduction of Cu(ΙΙ)-Coordination [O] . Guangtao Qian, Mengjie Hu, Shangying Zhang, 2020

機譯：通過引入Cu（III）-配位合成具有增強的介電常數的耐高溫聚酰亞胺
7. Modified halloysite nanotube filled polyimide composites for film capacitors: high dielectric constant, low dielectric loss and excellent heat resistance [O] . Tianwen Zhu, Chao Qian, Weiwen Zheng, 2018

機譯：用于薄膜電容器的改進的Halloysite納米管填充聚酰亞胺復合材料：高介電常數，低介電損耗和優異的耐熱性

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Improved planarization techniques applied to a low dielectric constant polyimide used in multilevel metal ICs

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